Quelltext der Seite Mc-pinout-2g4radio


====== I_UfE_Ag_2g4radio ======

======meschnetics anschlußbelegung======
===== ZDM-A1281-A2 PinOUT vs. embedded ATmega1281 und AT86RF230 =====
{| border="1"
|-
!Pin
!ZDM-A1281-A2
!Pin
!ATmega1281
|-
|1	
|SPI_CLK	
|11	
|PB1 (SCK/PCINT1)	
|-
|2	
|SPI_MISO	
|13	
|PB3 (MISO/PCINT3)	
|-
|3	
|SPI_MOSI	
|12	
|PB2 (MOSI/PCINT2)	
|-
|4	
|GPIO0
|15	
|PB5 (OC1A/PCINT5)	
|-
|5	
|GPIO1
|16	
|PB6 (OC1BPCINT6)	
|-
|6	
|GPIO2
|17	
|PB7 (OC0A/OC1C/PCINT7)	
|-
|7	
|OSC32K_OUT	
|18	
|PG3 (TOSC2)	
|-
|8	
|RESET	
|20	
|RESET	
|-
|9	
|DGND	
|22	
|GND	
|-
|10	
|CPU_CLK	
|24	
|XTAL1	
|-
|11	
|I2C_CLK	
|25	
|PD0 (SCL/INT0)	
|-
|12	
|I2C_DATA	
|26	
|PD1 (SDA/INT1)	
|-
|13	
|UART_TXD	
|27	
|PD2 (TXD1/INT2)	
|-
|14	
|UART_RXD	
|28	
|PD3 (RXD1/INT3)	
|-
|15	
|UART_RTS	
|29	
|PD4 (ICP1)	
|-
|16	
|UART_CTS	
|30	
|PD5 (XCK1)	
|-
|17	
|GPIO6	
|31	
|PD6 (T1)	
|-
|18	
|GPIO7	
|32	
|PD7 (T0)	
|-
|19	
|GPIO3	
|33	
|PG0 (WR)	
|-
|20	
|GPIO4	
|34	
|PG1 (RD)	
|-
|21	
|GPIO5	
|43	
|PG2 (ALE)	
|-
|22	
|DGND	
|22	
|GND	
|-
|23	
|DGND	
|22	
|GND	
|-
|24	
|D_VCC	
|21	
|VCC	
|-
|25	
|D_VCC	
|21	
|VCC	
|-
|26	
|JTAG-TMS	
|56	
|PF5 (ADC5/JTAG-TMS)	
|-
|27	
|JTAG-TDI	
|54	
|PF7 (ADC7/JTAG-TDI)	
|-
|28	
|JTAG-TDO	
|55	
|PF6 (ADC6/JTAG-TDO)	
|-
|29	
|JTAG-TCK	
|57	
|PF4 (ADC4/JTAG-TCK)	
|-
|30	
|ADC_INPUT_3
|58	
|PF3 (ADC3)	
|-
|31	
|ADC_INPUT_2	
|59	
|PF2 (ADC2)	
|-
|32	
|ADC_INPUT_1
|60	
|PF1 (ADC1)	
|-
|33	
|BAT	
|61	
|PF0 (ADC0)	
|-
|34	
|A_VREF	
|62	
|AREF	
|-
|35	
|AGND	
|63	
|GND	
|-
|36	
|GPIO_1WIRE	
|1	
|PG5 (OC0B)	
|-
|37	
|UART_DTR	
|6	
|PE4 (OC3B/INT4)	
|-
|38	
|USART0_RXD	
|2	
|PE0 (RXD0/PCINT8/PDI)	
|-
|39	
|USART0_TXD	
|3	
|PE1 (TXD0/PD0)	
|-
|40	
|USART0_EXTCLK	
|4	
|PE2 (XCK0/AIN0)	
|-
|41	
|GPIO8	
|5	
|PE3 (OC3A/AIN1)	
|-
|42	
|IRQ7	
|9	
|PE7 (ICP3/CLK0/INT7)	
|-
|43	
|IRQ6	
|8	
|PE6 (T3/INT6)	
|}
Desweiteren sind intern noch folgende Pins des AT86RF230 mit Pins des ATmega1281 verbunden:
{| border="1"
|-
!Pin
!AT86RF230
!Pin
!ATmega1281
|-
|7	
|TST	
|n.v.	
|GND	
|-
|8	
|RST	
|44	
|PA7 (AD7)
|-
|11	
|SLP_TR	
|14	
|PB4 (OC2A/PCINT4)
|-
|17	
|CLKM
|24	
|XTAL1
|-
|19	
|SCLK	
|11	
|PB1 (SCK/PCINT1)
|-
|20	
|MISO	
|13	
|PB3 (MISO/PCINT3)
|-
|22	
|MOSI	
|12	
|PB2 (MOSI/PCINT2)
|-
|23	
|SEL	
|10	
|PB0 (SS/PCINT0)
|-
|24	
|IRQ	
|7	
|PE5 (OC3C/INT5)
|}
http://www.atmel.com/dyn/resources/prod_documents/doc8117.pdf (der Schaltplan auf Seite 12 in [[1]])\n[[category:DWImport]]\n